SDU Microelectronics presents new STT-RAM Logic-in-Memory research at IEEE SOCC 2026

The research

The work presents a unified Logic-in-Memory (LiM) architecture for Spin-Transfer Torque RAM (STT-RAM), enabling OR/NOR, AND/NAND, and XOR/XNOR logic operations to be performed directly within standard STT-RAM memory cells. Importantly, the proposed approach does not require structural modifications to conventional STT-RAM arrays, supporting compact integration of computation and memory. The design targets reduced delay and hardware overhead while maintaining competitive energy efficiency, contributing toward scalable in-memory computing systems that reduce costly data movement between processors and memory.

The paper was authored by Pegah Shafaghi, Yasser Rezaeiyan, Sonal Shreya, Farshad Moradi, and Hooman Farkhani, bringing together researchers from the University of Southern Denmark and Aarhus University.

At IEEE SOCC 2026

The work was presented during the technical session “TS4: Devices and Platforms for Edge and Accelerated AI/ML Computing I”, chaired by Hooman Farkhani on September 30. The session brought together research on emerging devices, computing platforms, and architectures for efficient edge and AI systems—a topic closely aligned with SDU Microelectronics' activities in emerging memories and energy-efficient computing.

About the paper

• Title: Efficient Logic-in-Memory Design for STT-RAM
• Authors: Pegah Shafaghi, Yasser Rezaeiyan, Sonal Shreya, Farshad Moradi and Hooman Farkhani
• Conference: 39th IEEE International System-on-Chip Conference (IEEE SOCC 2026), Heidelberg, Germany, 30 September – 2 October 2026
• Session: TS4: Devices and Platforms for Edge and Accelerated AI/ML Computing I

Read more about SDU Microelectronics' research in Advanced Computing.

Read also: First SDU Microelectronics publication on probabilistic computing presented at IEEE SOCC 2026