First SDU Microelectronics publication on probabilistic computing presented at IEEE SOCC 2026

The research

The paper, “Efficient FPGA Architectures for Probabilistic Computing Using P-Bit Networks,” investigates how probabilistic computing systems based on stochastic P-bits can be efficiently implemented and scaled on FPGA hardware.

The work compares group-parallel and time-multiplexed implementations and introduces a time-multiplexed architecture with parallel summation to reduce the latency caused by sequential memory accesses. It also employs compressed sparse row (CSR) representation of the P-bit coupling matrix and processes this representation directly in hardware without reconstructing the dense matrix. This becomes increasingly important as the networks scale: the studied coupling matrices increase from approximately 70% sparsity for a 12-P-bit circuit to 99.93% for an 8367-P-bit circuit.

Demonstrated on FPGA hardware

Implemented on a Zybo Z7-10 FPGA, the proposed architecture was demonstrated using probabilistic multiplier/factorizer circuits, illustrating both forward and inverse computation. The study provides an FPGA-based platform for exploring scalable P-bit architectures and creates a foundation for future work toward larger probabilistic processors and implementations using energy-efficient stochastic devices.

The paper was authored by Mads Eifer, Thomas S. Christiansen, Simon Richter, Dario Fernández Khatiboun, Farshad Moradi, and Hooman Farkhani, reflecting collaboration between the University of Southern Denmark and Aarhus University.

At IEEE SOCC 2026

The paper was presented in TS6: Emerging and Disruptive Technologies I, a session focused on novel computing paradigms and hardware technologies beyond conventional architectures. This setting was particularly relevant for the work, which represents SDU Microelectronics’ first published contribution in probabilistic computing and supports the group’s broader activities in emerging and unconventional computing.

About the paper

• Title: Efficient FPGA Architectures for Probabilistic Computing Using P-Bit Networks
• Authors: Mads Eifer, Thomas S. Christiansen, Simon Richter, Dario Fernández Khatiboun, Farshad Moradi and Hooman Farkhani
• Conference: 39th IEEE International System-on-Chip Conference (IEEE SOCC 2026), Heidelberg, Germany, 30 September – 2 October 2026
• Session: TS6: Emerging and Disruptive Technologies I

Read more about SDU Microelectronics' research in Advanced Computing.

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